1. Field of the Invention
The present invention relates to a semiconductor memory device such as a semiconductor memory device using a ferroelectric capacitor for memory cells.
2. Related Art
A ladder ferroelectric RAM (Random Access Memory) includes plate lines corresponding to bit lines provided in respective memory cell columns. Furthermore, such a ferroelectric RAM includes at least one reset line for resetting all memory cells in a cell array. Accordingly, if the number of bit lines is k in a certain cell array, k plate lines and at least one reset line are necessary. Namely, to drive a cell array including memory cells in k columns, the sum of the number of plate lines and that of reset lines is equal to or greater than (k+1).
If the numbers of plate lines and reset lines are large, an area of wirings for these lines is disadvantageously made large. Further, if the numbers of plate lines and reset lines are large, circuits for driving these lines are disadvantageously made large in scale.